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Thesis defences

PhD Oral Exam - Neetusha Kalarikkal, Electrical and Computer Engineering

Emulation of Faults in Permanent Magnet Synchronous Machines


Date & time
Friday, July 18, 2025
10 a.m. – 1 p.m.
Cost

This event is free

Organization

School of Graduate Studies

Contact

Dolly Grewal

Accessible location

Yes

When studying for a doctoral degree (PhD), candidates submit a thesis that provides a critical review of the current state of knowledge of the thesis subject as well as the student’s own contributions to the subject. The distinguishing criterion of doctoral graduate research is a significant and original contribution to knowledge.

Once accepted, the candidate presents the thesis orally. This oral exam is open to the public.

Abstract

Permanent magnet synchronous machines (PMSMs) are used in electric vehicles because they are compact, highly efficient, and have high dynamic performance. High reliability and fault tolerance are required for these applications. When exposed to mechanical stress, moisture, and high temperatures, electric machines can suffer from various faults. One of the more common and primarily catastrophic faults in PMSMs is the inter-turn short circuit fault in a stator coil. Hence, PMSM behaviour should be studied in the event of this fault.

It is essential to have a machine model that is accurate enough to study such fault scenarios. An advancement of this idea is to develop a power electronic setup that emulates the PMSM machine fault in real-time. Power hardware-in-the-loop (PHIL) simulation, also called emulation, is the real-time simulation of a device under test (DUT) involving rated voltage, current, and power levels of the DUT. For the emulation of an electric machine, a power electronic converter is used to mimic the machine in real-time for all static and dynamic conditions. An emulator can replace a physical machine during the testing and development stages of the drive inverter. PHIL emulation provides a safer and more flexible development environment. It gives the advantage of testing the drive inverter before the machine is prototyped. In addition, the emulator can simulate various loading conditions. Thus, the drive inverter can be tested at different power levels without a prototype of the machine. Since no mechanical drive train is needed for such a test, an emulator setup can reduce the cost of testing in terms of space, safety enclosures, and maintenance requirements.

The accurate emulation of the machine faults will pave the way for developing robust fault-tolerant control techniques for the inverter under test. In addition, the PHIL emulation helps avoid creating expensive physical damage to a motor when conducting studies regarding fault. This research proposes to do the PHIL emulation of a PMSM with an ITSC fault. The analytical model developed is used in the emulator setup. This research proposes using a proportional-integral resonant (PIR) controller instead of the traditional proportional-integral (PI) controller to increase the accuracy of the current drawn by the PHIL emulator in the event of a fault.

One application of this study is in electric power steering (EPS) motors. An EPS motor provides an assist torque for steering the vehicle based on the torque the driver applies to the steering wheel. A permanent magnet synchronous motor (PMSM) is the best fit for power steering because of the smaller size, lighter weight, and sinusoidal back-emf of a PMSM. These characteristics make PMSM suitable for reasonable torque control. However, a PMSM can eventually develop a stator inter-turn short circuit (ITSC) fault, which can cause a ripple in the assist torque produced by the EPS motor, thus leading to a possible catastrophe. Power hardware-in-the-loop (PHIL) emulation of this fault can help to replicate the scenario within the laboratory environment by drawing the rated current and rated power in real-time. This research proposes to study the PHIL emulation of the specific case of an EPS motor operating under torque control mode.

Another research area that needs to be focused on is the elimination or reduction of common-mode current when the drive inverter and the emulating converter are connected to a common DC power supply. In a conventional emulator setup, isolated DC power supplies are used for the drive inverter and the emulating converter to prevent circulating common-mode currents. The emulating converter side requires a power supply with bidirectional power flow capability. Generally, an active front-end converter (AFEC) is used to realize this power source. Suppose the emulating converter and the drive inverter are connected to a common DC power supply, the power circulates within these converters, and the DC supply can be a simple unidirectional power supply that provides for the losses. The complexity in the emulator hardware setup is reduced because the front-end converter and its associated control will not be needed in such a case. However, circulating common-mode currents will distort the emulator current while operating with the same DC bus. The elimination or reduction of this common mode current is one of the objectives of this thesis.

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