PhD Oral Exam - Di Zhang, Electrical and Computer Engineering

When studying for a doctoral degree (PhD), candidates submit a thesis that provides a critical review of the current state of knowledge of the thesis subject as well as the student’s own contributions to the subject. The distinguishing criterion of doctoral graduate research is a significant and original contribution to knowledge.

Once accepted, the candidate presents the thesis orally. This oral exam is open to the public.

Abstract

This dissertation presents the design and experimental validation of several high-speed mixed-signal complementary metal-oxide-semiconductor (CMOS) transmitters for optical links.

Vertical-cavity surface-emitting lasers (VCSELs) are widely employed in short-reach optical links due to their compact size and compatibility with CMOS integration. Conventional VCSEL drivers involve a trade-off between power consumption and circuit complexity. To improve energy efficiency, a pull-down driver is proposed, while a 3-tap feed-forward equalizer (FFE) is employed to compensate for VCSEL nonlinearity. Since the average utilization of data-center links is typically below 20%, burst-mode operation is adopted to further reduce system power consumption. Measurement results demonstrate 10-Gb/s operation with a turn-on time of 3.7 ns.

For longer-reach optical links, micro-ring modulators (MRMs) are promising candidates despite the challenges associated with temperature stabilization. MRMs require high modulation voltages and exhibit voltage-dependent nonlinearities. A stacked transistor topology is employed to accommodate a 3.8-Vpp output swing and ensure device reliability. A linear driver architecture is proposed to support both non-return-to-zero (NRZ) and pulse-amplitude modulation four-level (PAM4) signaling. Input electrical channel loss is compensated using a continuous-time linear equalizer (CTLE). Active inductors are implemented at the output to mitigate MRM nonlinearity for NRZ signaling. Measurement results demonstrate a 12-Gb/s electrical eye and a 7-Gb/s optical eye.

In addition, a dual-channel half-rate driver for a two-segment MRM is proposed to generate PAM4 signals in the optical domain, thereby reducing equalization complexity. A duty-cycle correction (DCC) circuit ensures a precise 50% clock duty cycle to maintain signal integrity, and a high-speed 2-to-1 multiplexer (MUX) serializes half-rate data streams into a full-rate signal for the output stage. Simulation results demonstrate operation at 16 Gb/s.