PhD Oral Exam - Abhijit Choudhury, Electrical & Computer Engineering

When studying for a doctoral degree (PhD), candidates submit a thesis that provides a critical review of the current state of knowledge of the thesis subject as well as the student’s own contributions to the subject. The distinguishing criterion of doctoral graduate research is a significant and original contribution to knowledge.

Once accepted, the candidate presents the thesis orally. This oral exam is open to the public.

Abstract

Recent research trends in power electronics modules are to increase the power density of the system for the same output power level and to increase the reliability of the system. One way to achieve this is by reducing the number of passive components in the system, while another way is to reduce the system losses. Electric and plug-in hybrid electric vehicles (EVs/PHEVs) are alternatives to internal combustion engine (ICE) vehicles. EVs have zero carbon emissions compared to the ICE vehicles.

Almost all EV electronic parts manufacturers utilize 2-level DC/AC inverters, driving a permanent-magnet synchronous machine (PMSM) for EVs, 2-level DC/AC inverters pose a problem with higher device losses when the switching frequency increases, which is governed by the thermal limitation of the switches. This problem is more prominent when the DC-link voltage is greater than the standard 275-400V DC (such as in an EV transit bus application), where the DC bus voltage could be as high as 400-600V DC. Thus, switching device voltage ratings need to be increased, in order to handle this high DC voltage range.

Moreover, to reduce the torque ripple and passive component size in the inverter, switching frequency needs to be increased, which leads to higher switching losses. To overcome the problem of inefficient DC bus voltage utilization (for greater than 400V DC) as well as to reduce the switching losses at higher frequencies, a 3-level, neutral point clamped (NPC) DC/AC inverter could be a potential solution. Although, NPC DC/AC inverters are popular in both high-power as well as medium-power drives, it has not yet been proposed or used in EV drives. One key challenge is the stability related to DC-link voltage balancing, especially during drive transients (quick acceleration and rapid braking) as well as in steady-state.

Developments of smart control algorithms, which take care of the DC-link voltage balancing, are extremely crucial. This is achieved in this research without using separate hardware to balance the two DC-link capacitor voltages, and at the same time utilizes regular PWM drive techniques. In this thesis, different space vector and carrier based DC-link voltage balancing topologies, with reduced switching frequency, has been proposed.

The proposed methodology takes care of the serious DC bus voltage balancing issue. A detailed comparative study has been carried out with a 2-level inverter, to show the performance improvement. Simulation and experimental studies are also carried out to show the efficacy of the proposed control strategies.