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Thesis defences

PhD Oral Exam - Sivanagaraju Gangavarapu, Electrical and Computer Engineering

Analysis and Design of Discontinuous Conduction Mode AC-DC Power Factor Correction Converters

Date & time

Friday, March 27, 2020
1 p.m. – 4 p.m.

Cost

This event is free

Organization

School of Graduate Studies

Contact

Jennifer Sachs

Where

Online

When studying for a doctoral degree (PhD), candidates submit a thesis that provides a critical review of the current state of knowledge of the thesis subject as well as the student’s own contributions to the subject. The distinguishing criterion of doctoral graduate research is a significant and original contribution to knowledge.

Once accepted, the candidate presents the thesis orally. This oral exam is open to the public.

Abstract

In more electric aircrafts (MEAs), the synchronous generators are connected directly to the turbo-engine to develop constant voltage variable frequency (CVVF) AC supply bus. In addition, the MEA has adopted high voltage DC bus in its power system to cater the various categories of load used by aircraft. Therefore, the MEA requires AC-DC power converters to convert CVVF AC to constant DC. Existing diode-bridge based passive multi-pulse AC-DC converters are suffering from heavy and bulky low frequency 350 Hz transformers, poor input power quality, low efficiency and unregulated output voltage. To overcome these drawbacks, this thesis work proposes and studies several new active switched-mode AC-DC converters (isolated and non-isolated) strictly satisfying the enhanced requirements of the aircraft application. The vital constituent in active AC-DC power conversion is the power factor correction (PFC). Understanding the certain limitations of the continuous conduction mode (CCM) operation for CVVF AC supply, the proposed converters are designed to operate in discontinuous conduction mode (DCM) to make use of its obvious benefits such as inherent PFC, reduced number of sensors, simple control, inherent zero current turn-on of the switches, and inherent zero diode reverse recovery losses. A single sensor based simple voltage control loop is only used to obtain the tightly regulated output voltage, which makes it economical, and improves the system reliability and robustness to high-frequency noise.

At first, a three-phase modular single-stage-isolated Cuk converter is proposed on considering Cuk converter merits such as inrush current limitation, no input filter requirement, and easy implementation of high frequency transformer isolation. The phase-modular converters are easy to implement, can be paralleled easily for high power design, operational with two-phase loss, and provide quick repair and maintenance. However, they employ more number of components and suffering from higher conduction losses. To overcome these issues, a new direct three-phase non-isolated Cuk-derived PFC converter with reduced number of components and conduction losses is proposed. With this new topology, the conduction losses are significantly reduced and efficiency is improved by 4 % compared to the previously analyzed phase-modular converter. However, this converter needs two DC-link capacitors for its operation at DC output that added extra capacitive losses. Further to reduce the capacitive losses, a new direct three-phase non-isolated buck-boost-derived PFC converter with one DC-link capacitor and reduced capacitive losses, along with retention of all the benefits of Cuk-derived PFC converter is proposed. For high power operations, interleaved topology of the three-phase buck-boost-derived PFC converter with reduced filter size, reduced losses, and improved efficiency is proposed. Finally, an isolated topology of the three-phase buck-boost-derived PFC converter with a novel clamping circuit to capture and utilize the transformers leakage inductance energy in order to improve the converter efficiency is proposed. The converters steady-state operation, DCM condition, and design equations are reported in detail. The small-signal models for all the proposed topologies using average current injected equivalent circuit approach are developed, and a detailed closed-loop controller design is illustrated. The simulation results from PSIM 11.1 software and the experimental results from proof-of-concept laboratory hardware prototypes are provided in order to validate the report analysis, design, and performance.

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